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3D Qualcomm SoC has tested on horizon

  • Author:Abby
  • Release on:2015-04-17

An illustration of Qualcomm’s expected fabrication process for its 3D VLSI or 3DV chipmaking process. 

(Image source: EE Times, Qualcomm)

The future of 3D very large scale integration or VLSI for SoCs will not stack die connected by through-silicon-vias or TSVs, but will build them on a single layered die, according to Karim Arabi, vice president of engineering at Qualcomm, at the International Symposium on Physical Design.

"Our 3D VLSI technology, which we call 3DV, enables die size to be shrunk in half, while simultaneously increasing yields," Arabi told EE Times.

Qualcomm's motivation, according to Arabi, is market share in the 18 billion smartphones that he predicts will be produced by 2018 — "more than all the computers and other electronic devices combined," he said. He also noted that even though the cloud is offloading some computationally intensive applications, such as speech recognition, there will still be an increasing need for local processing power for most smartphone functions.

In the long term, Qualcomm is building neural processing units or NPUs modeled on the human brain, "because they are highly flexible and highly efficient for the next generation of mobile devices, cloud computing, big data processing, deep learning and machine learning," Arabi said. But for the near term, Qualcomm is extending the capabilities of its already popular SoCs with a new type of 3DV interconnection and process technology.